The present disclosure generally relates to the simulation/verification of Hardware Description Language (HDL) based circuit designs (e.g., Application-Specific Integrated Circuit (ASIC) or Field-Programmable Gate Array (FPGA) circuit designs). Such HDL based circuit designs often include different types of clocks. For example, an HDL based circuit design can include synchronous clocks, synchronous derivative clocks, and asynchronous clocks. A clock is considered synchronous when a source element and a destination element have the same clock. When a source element and a destination element have different clocks that are derived from the same source, the clocks are considered synchronous derivate clocks. When a source clock and a destination clock originate from different clocking elements, the source and destination clocks are considered asynchronous. Asynchronous clocks can have the same or a different frequency.